COMPUTER AND DIGITAL LOGIC - 2019/0
Module code: EEE1033
Module Overview
Expected prior learning: None specifically advised.
Module purpose: This course offers an introduction to the principles of digital logic covering both the theory (e.g. logical operators, their combination and simplification, and basic logic circuit arrangements such as counters & registers) and the practical implementation of logic flows within software. The latter serves also as an introduction to the principles of programming through the Python language.
Module provider
Electrical and Electronic Engineering
Module Leader
DIKAIOS Nikolaos (Elec Elec En)
Number of Credits: 15
ECTS Credits: 7.5
Framework: FHEQ Level 4
Module cap (Maximum number of students): N/A
Overall student workload
Module Availability
Semester 1
Prerequisites / Co-requisites
None
Module content
Indicative content includes the following.
Part A: Logic and Digital Electronics (weeks 1-11)
Principles: digital signals and systems, computer hardware and basic operation. Symbolic logic, logical connectives: AND, OR, NAND, NOR, EXOR. Boolean algebra, duality, truth tables, positive & negative logic. Electronic logic gates: FET logical switch and CMOS. Combinational logic functions. Minimisation using Karnaugh maps and algorithmic techniques. Propagation delay and logic hazards.
[10 lectures]
Simple binary arithmetic: codes and conversions, 2’s complement and floating point representation. Arithmetic circuits: series/parallel adders and subtractors.
[3 lectures]
IC logic systems: multiplexers, decoders, programmable logic devices. Latches and flip-flops: clocked D-type and JK-type, edge and pulse triggered versions. Shift registers and counters. Synchronous sequential systems: state diagrams and design method.
[9 lectures]
Part B: Logic in Software (weeks 5-8)
* Fundamentals of procedural programming (in Python). Functions. Scope and Extent. Basic console and file I/O.
[2 lectures, 3 double-labs]
* Conditionals. Logic and its implementation as if/for/while preconditions (AND, OR, NOT)
* Procedural control: sequence and selection (looping constructs, iteration and recursion)
[2 lectures, 3 double-labs]
Assessment pattern
| Assessment type | Unit of assessment | Weighting |
|---|---|---|
| Examination | 2-HOUR, CLOSED-BOOK WRITTEN EXAMINATION, ASSESSING DIGITAL LOGIC (PART A) | 75 |
| Practical based assessment | ASSESSED LAB EXERCISES: 2 PYTHON-BASED EXERCISES (COVERING 3 DOUBLE-HOUR LABS) | 15 |
| Oral exam or presentation | TUTORIAL PEER ASSESSMENT SCHEME (TPAS) | 10 |
Alternative Assessment
Not applicable: students failing a unit of assessment resit the assessment in its original format.
Assessment Strategy
The assessment strategy for this module is designed to provide students with the opportunity to demonstrate the following.
That they can design, construct, comprehend and manipulate common digital logic arrangements in both hardware and software.
That they can design and implement simple programs in a procedural programming language.
Thus, the summative assessment for this module consists of the following.
Examination (covering Part A of the syllabus) 75%
Python programming exercises in labs (covering Part B of the syllabus) 15% (weeks 8-11)
Digital Logic Questions contributing to the cross-module Y1 Tutorial Peer Assessment Scheme (TPAS) 10%
The examination consists of 2h closed-book written examination. There are 5 questions each from different area of Part A of the course. Each question consists of several subquestions testing knowledge, analytical, and design skills.
The lab assessments consists of writing short Python programs in the two-hour long lab sessions running toward the end of the semester. The lab sessions will provide both learning opportunities and assessment vehicles being supported by experienced lab demonstrators.
Formative assessment and feedback
For the module, students will receive formative assessment/feedback in the following ways.
During lectures, by question and answer sessions
During supervised computer laboratory sessions
Module aims
- The aim of this module is to offer an introduction to the principles of digital logic to support both the design & analysis of simple digital circuits and systems, and the implementation of short programs and control flows.
Learning outcomes
| Attributes Developed | ||
| 1 | Be able to demonstrate an understanding of the principles of digital logic with a sound grounding of the theory behind these | K |
| 2 | Be able to choose and combine appropriate logical operators to solve problems and create common arrangements (such as counters & registers) using gates & flip-flops. | KCP |
| 3 | Be able to implement and solve problems in digital logic within a software program. | KCT |
Attributes Developed
C - Cognitive/analytical
K - Subject knowledge
T - Transferable skills
P - Professional/Practical skills
Methods of Teaching / Learning
The learning and teaching strategy is designed to achieve the following aims.
To introduce the basic building blocks of digital logic circuits and provide a solid underpinning of the theory behind their operation and common combinations to enable the design and implementation of digital electronic circuits. The topics covered include Boolean Logic and Gates, Latches and Flip-Flops, Counters.
To introduce basic binary representations of data including binary forms of integers including negative numbers (one and two’s complement) and floating point representation.
Students learn to identify, describe classify and simplify the operation of basic logic circuits performance of software systems and components through the use of analytical methods.
Students learn basic programming skills and functional thinking enabling the abstraction of logic statements from problem specifications and implementation of these in software form (specifically, Python).
Learning and teaching methods include the following.
Lectures: Weeks 1-11 for 2 hours per week.Weeks 8-11 for 1 hour per week = 26 hours total
2 hour Labs: Python exercises to consolidate the lecture material from weeks 8-11 = 8 hours total
Indicated Lecture Hours (which may also include seminars, tutorials, workshops and other contact time) are approximate and may include in-class tests where one or more of these are an assessment on the module. In-class tests are scheduled/organised separately to taught content and will be published on to student personal timetables, where they apply to taken modules, as soon as they are finalised by central administration. This will usually be after the initial publication of the teaching timetable for the relevant semester.
Reading list
https://readinglists.surrey.ac.uk
Upon accessing the reading list, please search for the module using the module code: EEE1033
Programmes this module appears in
| Programme | Semester | Classification | Qualifying conditions |
|---|---|---|---|
| Electronic Engineering with Computer Systems BEng (Hons) | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electrical and Electronic Engineering MEng | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electronic Engineering with Space Systems MEng | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electronic Engineering BEng (Hons) | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electrical and Electronic Engineering BEng (Hons) | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electronic Engineering with Nanotechnology BEng (Hons) | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electronic Engineering with Nanotechnology MEng | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Computer and Internet Engineering BEng (Hons) | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electronic Engineering with Space Systems BEng (Hons) | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electronic Engineering with Computer Systems MEng | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Electronic Engineering MEng | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
| Computer and Internet Engineering MEng | 1 | Compulsory | A weighted aggregate mark of 40% is required to pass the module |
Please note that the information detailed within this record is accurate at the time of publishing and may be subject to change. This record contains information for the most up to date version of the programme / module for the 2019/0 academic year.