ELECTRICAL SCIENCE II - 2020/1
Module code: EEE2045
In light of the Covid-19 pandemic, and in a departure from previous academic years and previously published information, the University has had to change the delivery (and in some cases the content) of its programmes, together with certain University services and facilities for the academic year 2020/21.
These changes include the implementation of a hybrid teaching approach during 2020/21. Detailed information on all changes is available at: https://www.surrey.ac.uk/coronavirus/course-changes. This webpage sets out information relating to general University changes, and will also direct you to consider additional specific information relating to your chosen programme.
Prior to registering online, you must read this general information and all relevant additional programme specific information. By completing online registration, you acknowledge that you have read such content, and accept all such changes.
Expected prior/parallel learning: None
Module purpose: All modern electronic devices make use of transistor technology and their future developments, via Moore’s Law and beyond, are fundamentally linked to device architecture. This module will introduce modern CMOS transistor structures and link to the operation for integrated circuits and modern memory devices. The module will also show how electric and magnetic fields can be unified within Maxwell’s equations to produce electromagnetic theory and solve common problems.
Electrical and Electronic Engineering
CAREY James (Elec Elec En)
Number of Credits: 15
ECTS Credits: 7.5
Framework: FHEQ Level 5
JACs code: H600
Module cap (Maximum number of students): N/A
Prerequisites / Co-requisites
Indicative content includes the following.
Part A - Digital Integrated Circuits (Dr David Carey)
Introduction, Moore’s Law and engineering overview. Logic Inversion and the voltage transfer characteristic. Complementary switches.
The MOSFET transistor: Structure, operation and electrical characteristics. Process and Device transconductance parameters.
The CMOS inverter: Static and dynamic performance and their relationship to structure, transistor operating regimes. Design criteria including matched transistors, propagation delay and transistor buffering, Power-delay and Energy-delay product, Introduction to device scaling.
CMOS Combinational Logic: NOR, NAND implementation. Transistor sizing design rules. CMOS transmission gate and CMOS Schmitt trigger gate.
Alternatives to CMOS Logic: Ratioed and ratioless design, pseudo-NMOS and dynamic logic CMOS.
Sequential CMOS Logic: Bistable circuits, CMOS implementation of flip-flop and counters.
CMOS based memory: Static random access memory (6T-SRAM). Structure and operation Dynamic RAM memory cell.
MOSFET based memory: Programmable Read Only Memory (PROM), Erasable PROM (EPROM), Electrically Erasable (E2PROM) and Flash memories.
Interconnects: models and sources of delay.
Revision sessions will also be included.
Part B - Electromagnetic Theory (Professor Ravi Silva)
Principle of superposition, grad V, del operator, free charges, conductors, electric flux density D, Gauss’ law
Point form of Gauss' law, Laplace’s equation
Capacitance, dielectrics, polarisation, permittivity, loss mechanisms in materials
Magnetic field and flux density B, permeability, ferromagnetic materials.
B-H loop, loss mechanisms, magnetic circuits
Ampere's circuital law, H inside and outside a conductor, point form and curl H
Boundary conditions for magnetic fields
Maxwell equations and electromagnetic theory.
|Assessment type||Unit of assessment||Weighting|
|Examination||2 HOUR CLOSED-BOOK WRITTEN EXAM||100|
Not applicable: students failing a unit of assessment resit the assessment in its original format.
The assessment strategy for this module is designed to provide students with the opportunity to demonstrate the learning outcomes.
The 2 hour written examination will assess knowledge of fundamental material properties and their behaviour in electric or magnetic fields; allow the student to demonstrate an ability to perform numerical calculations of key material and device parameters. The assignment will assess the student’s ability to research into CMOS electronic devices.
Thus, the summative assessment for this module consists of the following:
A 2-hour closed book written examination
Formative assessment and feedback
For the module, students will receive formative assessment/feedback in the following ways.
During lectures, by question and answer sessions
During tutorials/tutorial classes
By means of unassessed tutorial problem sheets (with answers/model solutions) provided in the revision guide
Via the marking of written reports
Via assessed coursework
- There are two main aims associated with this module. The first is to introduce transistor structure and to show how the operation and electrical characteristics can be related to both current and future device architectures and material choice. The second aim is to show electromagnetic theory can be applied in radio frequency, high speed digital and microwave engineering and product design at circuit level.There are two main aims associated with this module. The first is to introduce transistor structure and to show how the operation and electrical characteristics can be related to both current and future device architectures and material choice. The second aim is to show electromagnetic theory can be applied in radio frequency, high speed digital and microwave engineering and product design at circuit level.
|1||Describe the properties and electrical characteristics of field effect transistor based devices.||KCT|
|2||Design the electrical and logic output of field effect transistor based devices to required performance specifications.||KCT|
|3||Describe the electric and magnetic field response of materials.||KCT|
|4||Describe electromagnetic wave propagation in different media.||KCT|
C - Cognitive/analytical
K - Subject knowledge
T - Transferable skills
P - Professional/Practical skills
Overall student workload
Independent Study Hours: 117
Lecture Hours: 33
Methods of Teaching / Learning
The learning and teaching strategy is designed to achieve the following aims.
1. Through the introduction of the key digital engineering and electromagnetic concepts, representative examples and in-class calculations, the students will be able to relate device structure to electrical characteristics.
2. Through the introduction, discussion and in-class examples of different transistor and device arrangements, students will be able to design networks to perform logical operations.
3. Through the use of a revision guide consisting of about 30 questions with full solutions, student will be able to pace their own learning in parallel with the lecture course.
4. Through a series of in-class formative tests, students will be able to readily judge their own progress in identify any gaps in their knowledge.
Learning and teaching methods include the following.
Lectures and class discussions, 27 hours (spread over 10 weeks)
Formative feedback sessions 3 hours (spread over 10 weeks)
Revision sessions 3 hours (week 11)
Indicated Lecture Hours (which may also include seminars, tutorials, workshops and other contact time) are approximate and may include in-class tests where one or more of these are an assessment on the module. In-class tests are scheduled/organised separately to taught content and will be published on to student personal timetables, where they apply to taken modules, as soon as they are finalised by central administration. This will usually be after the initial publication of the teaching timetable for the relevant semester.
Upon accessing the reading list, please search for the module using the module code: EEE2045
Programmes this module appears in
|Electronic Engineering with Computer Systems BEng (Hons)||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering BEng (Hons)||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electrical and Electronic Engineering BEng (Hons)||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Nanotechnology BEng (Hons)||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Nanotechnology MEng||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Space Systems BEng (Hons)||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Space Systems MEng||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electrical and Electronic Engineering MEng||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Computer Systems MEng||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering MEng||2||Compulsory||A weighted aggregate mark of 40% is required to pass the module|
Please note that the information detailed within this record is accurate at the time of publishing and may be subject to change. This record contains information for the most up to date version of the programme / module for the 2020/1 academic year.