DIGITAL DESIGN WITH VHDL - 2020/1
Module code: EEE3027
Module purpose: This module provides knowledge about advanced digital circuit design and the hardware description language VHDL. The practical part of the course is concerned with FPGA implementation, using modern CAD tools and FPGA prototyping boards.
Electrical and Electronic Engineering
BRIDGES Christopher (Elec Elec En)
Number of Credits: 15
ECTS Credits: 7.5
Framework: FHEQ Level 6
JACs code: H130
Module cap (Maximum number of students): N/A
Prerequisites / Co-requisites
Expected prior learning: This module builds in part on the compulsory Year 2 module EEE2045 – Engineering Science II.
Indicative content includes the following.
 Introduction. The evolution of VLSI circuits. The role of computer-aided design automation.
[2-4] Hardware Description Languages. Basics of VHDL. Domains and levels of modelling. System specification: Design units. Signals. Behavioural Modelling. Structural Modelling. Hierarchical modelling concepts. Components of a simulation. Testing a design with a Testbench. Lexical elements. Operators. Syntax descriptions – EBNF. Types. Assignments. Processes. Configurations. VHDL synthesis. Examples of VHDL code.
[5-6] Introduction to Design Assignment 1.
[7-14] Combinational logic design with VHDL. Decoders. Encoders. Three-state devices. multiplexers. Exclusive-OR gates and Parity Circuits. Comparators. Adders, Subtractors, and ALUs. Combinational multipliers. Examples.
[15-21] Sequential-circuit design with VHDL. Latches and flip-flops. Clocked synchronous state-machine design. Feedback sequential-circuit design. Counters. Shift registers. Introduction to Design Assignment 2.
[22-23] ASIC Design Methodologies and CAD Tools. Design automation and classes of design tools. Implementation approaches. Field-programmable gate arrays. Intellectual property cores. System-on-a-chip. Design synthesis and levels of abstraction.
 Revision lecture
Practical Work: The lecture course is accompanied by a set of laboratory exercises on digital design using the hardware description language VHDL. The laboratory work covers all stages of the FPGA design process and involves hands-on exposure to the CAD tools such as Xilinx ISE or Synplify and a prototyping board (containing a Xilinx Spartan-6 FPGA).
The practical component is used as a project-driven learning vehicle in the course. The students learn and discover new knowledge by carrying out design assignments. Being given the general principles of VHDL in lectures, they learn further details about the language and the design tools through hands-on experience being guided by computer-aided learning materials, design tutorials and laboratory supervision.
|Assessment type||Unit of assessment||Weighting|
|Coursework||COURSEWORK - DESIGN ASSESSMENTS||40|
|Examination||2 HOUR WRITTEN EXAMINATION||60|
Not applicable: students failing a unit of assessment resit the assessment in its original format.
The assessment strategy for this module is designed to provide students with the opportunity to demonstrate the following.
The assessments are designed to support the lectures on design principles as well as provide the hands on knowledge required to perform practical VHDL tasks. The two assignments each require a report in which students must concisely describe how the VHDL-code works, and how it is successfully implemented on an FPGA device. It will assess the student’s ability to debug, compile, and implement a full design with only guided support from supervisors.
Thus, the summative assessment for this module consists of the following.
· 2 hour close book written examination
· VHDL Assignment 1 involves writing, debugging, expanding and simulating of VHDL designs. 16 Pages due Tuesday, Week 5
· VHDL Assignment 2 which involves a further VHDL design which is then implemented and tested on the real FPGA hardware. 16 Pages due Tuesday Week 11.
Any deadline given here is indicative. For confirmation of exact date and time, please check the Departmental assessment calendar issued to you.
Formative assessment and feedback
For the module, students will receive formative assessment/feedback in the following ways.
· During lectures, by question and answer sessions
· During tutorials/tutorial classes
· By means of unassessed tutorial problem sheets (with answers/model solutions)
· During supervised software and hardware laboratory sessions
· Via the marking of written reports
· Via assessed coursework
- Develop understanding of digital circuit design using the hardware description language VHDL.
- Give insight into current approaches to application-specific integrated circuit (ASIC) implementation and typical design flows.
- Provide hands-on design experience with the main stages of a typical ASIC/FPGA design flow.
|1||Explain the principles of advanced digital circuit design||KC|
|2||Describe state-of-the-art ASIC/FPGA design methodologies .||KP|
|3||Build FPGA designs using the hardware description language VHDL||P|
|4||Operate, debug and analyse IP core designs in modern VHDL software tool-chains||P|
C - Cognitive/analytical
K - Subject knowledge
T - Transferable skills
P - Professional/Practical skills
Overall student workload
Independent Study Hours: 110
Lecture Hours: 24
Laboratory Hours: 24
Methods of Teaching / Learning
On successful completion of this module, students will be able to:
Explain the principles of advanced digital circuit design (C,K).
Describe state-of-the-art ASIC/FPGA design methodologies (K,P).
Build FPGA designs using the hardware description language VHDL (P).
Operate, debug and analyse IP core designs in modern VHDL software tool-chains (P).
Key to General Learning Outcomes: C-Cognitive/Analytical; K-Subject Knowledge; T-Transferable Skills; P- Professional/ Practical skills. For Engineering Council Specific Learning Outcomes, see table at end of form.
Indicated Lecture Hours (which may also include seminars, tutorials, workshops and other contact time) are approximate and may include in-class tests where one or more of these are an assessment on the module. In-class tests are scheduled/organised separately to taught content and will be published on to student personal timetables, where they apply to taken modules, as soon as they are finalised by central administration. This will usually be after the initial publication of the teaching timetable for the relevant semester.
Reading list for DIGITAL DESIGN WITH VHDL : http://aspire.surrey.ac.uk/modules/eee3027
Programmes this module appears in
|Electronic Engineering with Computer Systems BEng (Hons)||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Space Systems MEng||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering BEng (Hons)||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Nanotechnology BEng (Hons)||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Nanotechnology MEng||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Communication Systems BEng (Hons)||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Space Systems BEng (Hons)||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Computer Systems MEng||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering MEng||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering MSc||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Communication Systems MEng||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
|Electronic Engineering with Professional Postgraduate Year MSc||2||Optional||A weighted aggregate mark of 40% is required to pass the module|
Please note that the information detailed within this record is accurate at the time of publishing and may be subject to change. This record contains information for the most up to date version of the programme / module for the 2020/1 academic year.