Surrey University Stag

DIGITAL DESIGN WITH VHDL - 2023/4

Module code: EEE3027

Module Overview

Module purpose: This module provides knowledge about advanced digital circuit design and the hardware description language VHDL. The practical part of the course is concerned with FPGA implementation, using modern CAD tools and FPGA prototyping boards.

Module provider

Electrical and Electronic Engineering

Module Leader

BRIDGES Christopher (Elec Elec En)

Number of Credits: 15

ECTS Credits: 7.5

Framework: FHEQ Level 6

JACs code: H130

Module cap (Maximum number of students): 40

Overall student workload

Independent Learning Hours: 66

Lecture Hours: 11

Tutorial Hours: 11

Laboratory Hours: 30

Guided Learning: 10

Captured Content: 22

Module Availability

Semester 2

Prerequisites / Co-requisites

EEE2045 – Engineering Science II EEE2048 – Computer Algorithms and Architecture

Module content

Indicative content includes the following.

[1] Introduction. The evolution of VLSI circuits. The role of computer-aided design automation.

[2-6] Hardware Description Languages. Basics of VHDL. Domains and levels of modeling. System specification: Design units. Signals. Behavioural Modelings. Structural Modelings. Hierarchical modeling concepts. Components of a simulation. Testing a design with a Testbench. Lexical elements. Operators. Syntax descriptions – EBNF. Types. Assignments. Processes. Configurations. VHDL synthesis. Examples of VHDL code.

[7-14] Combinational logic design with VHDL. Decoders. Encoders. Three-state devices. multiplexers. Exclusive-OR gates and Parity Circuits. Comparators. Adders, Subtractors, and ALUs. Combinational multipliers. With Examples.

[15-21] Sequential-circuit design with VHDL. Latches and flip-flops. Clocked synchronous state-machine design. Feedback sequential-circuit design. Counters. Shift registers. With Examples.

[22-24] ASIC Design Methodologies and CAD Tools. Design automation and classes of design tools. Implementation approaches. Field-programmable gate arrays. Intellectual property cores. System-on-a-chip. Pipelining.

 

Practical Work: The lecture course is accompanied by a set of laboratory exercises on digital design using the hardware description language VHDL. The laboratory work covers all stages of the FPGA design process and involves hands-on exposure to the CAD tools such as Xilinx ISE and a prototyping board (containing a Xilinx Spartan-6 FPGA).


The practical component is used as a project-driven learning vehicle in the course. The students learn and discover new knowledge by carrying out the design assignments. Being given the general principles of VHDL in lectures, they learn further details about the language and the design tools through hands-on experience being guided by computer-aided learning materials, design tutorials and laboratory supervision.

Assessment pattern

Assessment type Unit of assessment Weighting
Coursework ASSIGNMENT 1 20
Coursework ASSIGNMENT 2 20
Coursework DESIGN ESSAY 60

Alternative Assessment

None

Assessment Strategy

The assessment strategy for this module is designed to provide students with the opportunity to demonstrate their developed understanding and learning of digital design techniques using VHDL.

The assessments are designed to support the lectures on design principles as well as provide the hands on knowledge required to perform practical VHDL tasks. The two assignments each require a report in which students must concisely describe how the VHDL-code works, and how it is successfully implemented on an FPGA device. It will assess the student’s ability to debug, compile, and implement a full design with only guided support from supervisors.

Thus, the summative assessment for this module consists of the following:

-         Assignment 1 involves writing, debugging, expanding and simulating of VHDL designs. 10 Pages due Tuesday, Week 6

-         Assignment 2 which involves a further VHDL design which is then implemented and tested on the real FPGA hardware. 10 Pages due Tuesday Week 10.

-         Final Essay that assesses design FPGA and ASIC concepts, methodologies and implementation considerations developed within the module.

Any deadline given here is indicative. For confirmation of exact date and time, please check the Departmental assessment calendar issued to you.

Formative assessment and feedback

For the module, students will receive formative assessment and feedback in the following ways.

-         During lectures and by question and answer sessions

-         During tutorials/tutorial classes

-         During supervised software and hardware laboratory sessions

-         Via the marking of written assignments.

 

Module aims

  • Develop understanding of digital circuit design using the VHDL hardware description language .
  • Give insight into typical FPGA design implementation concepts and the approaches for application-specific integrated circuit (ASIC).
  • Provide hands-on design experience with the Xilinx FPGA simulation, implementation and analysis tools.

Learning outcomes

Attributes Developed
001 Explain the principles of advanced digital circuit design  KC
002 Describe state-of-the-art ASIC/FPGA design methodologies KP
003 Build FPGA designs using the hardware description language VHDL    P
004 Operate, debug and analyse IP core designs in modern VHDL software tool-chains  P

Attributes Developed

C - Cognitive/analytical

K - Subject knowledge

T - Transferable skills

P - Professional/Practical skills

Methods of Teaching / Learning

On successful completion of this module, students will be able to:



  • Explain the principles of advanced digital circuit design (C,K).


  • Describe state-of-the-art ASIC/FPGA design methodologies (K,P).


  • Build FPGA designs using the hardware description language VHDL (P).


  • Operate, debug and analyse IP core designs in modern VHDL software tool-chains (P).

     



Key to General Learning Outcomes: C-Cognitive/Analytical; K-Subject Knowledge; T-Transferable Skills; P- Professional/ Practical skills. For Engineering Council Specific Learning Outcomes, see table at end of form.

Indicated Lecture Hours (which may also include seminars, tutorials, workshops and other contact time) are approximate and may include in-class tests where one or more of these are an assessment on the module. In-class tests are scheduled/organised separately to taught content and will be published on to student personal timetables, where they apply to taken modules, as soon as they are finalised by central administration. This will usually be after the initial publication of the teaching timetable for the relevant semester.

Reading list

https://readinglists.surrey.ac.uk
Upon accessing the reading list, please search for the module using the module code: EEE3027

Other information

This module has a capped number and may not be available to ERASMUS and other international exchange students. Please check with the International Engagement Office email: ieo.incoming@surrey.ac.uk

Programmes this module appears in

Programme Semester Classification Qualifying conditions
Electronic Engineering with Computer Systems BEng (Hons) 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering BEng (Hons) 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering with Nanotechnology BEng (Hons) 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering with Nanotechnology MEng 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering with Space Systems BEng (Hons) 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering with Space Systems MEng 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering with Professional Postgraduate Year MSc 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering MSc 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering with Computer Systems MEng 2 Optional A weighted aggregate mark of 40% is required to pass the module
Electronic Engineering MEng 2 Optional A weighted aggregate mark of 40% is required to pass the module

Please note that the information detailed within this record is accurate at the time of publishing and may be subject to change. This record contains information for the most up to date version of the programme / module for the 2023/4 academic year.